Semiconductor memory device and manufacturing method thereof

专利摘要:
In the fabrication of semiconductor memory devices, particularly in dynamic random access memory (DRAM) having an HSG-type stack capacitor structure, after the accumulation node forming silicon film is surface treated by HSG annealing process using dilute fluoric acid, the accessories and alignment regions In this manner, the accumulation node formation film is prevented from floating in the air on the sidewall surface of the accumulation node formation contact pattern, thereby preventing peeling which causes a decrease in yield. For this purpose, the accumulation node forming silicon film covers the sidewall surface of the contact pattern in the alignment region.
公开号:KR19980081520A
申请号:KR1019980013878
申请日:1998-04-17
公开日:1998-11-25
发明作者:마나베가즈따까
申请人:가네꼬히사시；닛뽕덴끼가부시끼가이샤；
IPC主号:

专利说明:

Semiconductor memory device and manufacturing method thereof
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a dynamic RAM (hereinafter referred to as DRAM) having a stacked capacitor structure in the form of a hexagonal grained (HSG). The invention also relates to a method of manufacturing a DRAM.
In the fabrication of DRAMs, each with a stack capacitor, HSG technology, which provides the surface of an accumulation node in the form of a silicon film with hemispherical grains, has recently been developed as one of a variety of ways to increase memory cell capacitors per unit area, which is bumpy Obtained by manufacturing the surface of the accumulation node in the form of a stack capacitor.
As disclosed in Japanese Patent Laid-Open No. 7-221034, in the HSG technique, the natural oxide film is removed from the surface of the silicon film by any method immediately before HSG treatment of the silicon film, and the natural oxide film is removed after the first natural oxide film is removed. It is important to form again.
Consequently, it is common practice to remove the native oxide film from the silicon film surface immediately before the HSG process and to treat the surface with diluted fluoric acid to terminate the silicon surface with hydrogen atoms.
The memory cell and the memory cell manufacturing method using the conventional HSG technology are shown in Figures 5a, 5b, 6a-6d, 7a, 7b, 8a, 8b, 9a and the accompanying drawings of this specification. This will be described with reference to FIG. 9B. First, FIG. 5A shows a layout of a memory cell. In FIG. 5A, reference numeral 101 denotes an isolation region, 102 and 103 a source drain region of the MOS transistor, 104 denotes a MOS transistor formed on the P-type silicon substrate 100 (bottom of FIG. 5B) via a gate oxide film. A gate electrode, 106 denotes a bit line, 107 denotes an accumulation node contact, 108 denotes an accumulation node. The entire cell area is covered with plate electrodes (described below in FIG. 8B).
Then, the memory cell manufacturing method will be described. 5B shows a MOS transistor formed on the p-type silicon substrate 100.
As shown in Fig. 6A, in order to ensure good flatness of the substrate surface, an insulating film of a boron-phospho-silicate glass (BPSG) film is formed by CVD and then heat treated. When the BPSG film 110 is in direct contact with the substrate 100, after the heat treatment, phosphorus (P) or boron (Bo) is diffused, resulting in the sheet resistance of the diffusion layer of the source drain region already formed and of the transistor already formed. The limit voltages deviate from their set values. As a result, a two-layer structure using a silicon oxide film as a lower layer is generally obtained.
A hole is then formed in the bit contact 105, and a twenty angstrom thick tungsten silicide film is also formed, so that the tungsten silicide film is patterned in a predetermined pattern to form the bit line 106.
Then, as shown in FIG. 6B, a second silicon oxide film 111 of 2000 angstroms is formed, and a second BPSG film 112 is formed to a thickness of 3000 angstroms, and a heat treatment at 900 ° C. is performed for the second BPSG film. It is executed to generate a reflow of 112 to maintain the flatness of the film surface. In addition, a third silicon oxide film of 2000 angstroms is formed.
The third embodiment oxide film 113 acts as a mask during the pretreatment (diluted fluoric acid) process immediately before the subsequent HSG process. In particular, since the etch rate of the BPSG film with dilute fluoric acid is about several times as large as the silicon oxide film, if the third silicon oxide film 113 does not have a thickness thick enough to be sufficiently used as a mask during the HSG pretreatment, the second BPSG film Most of the 112 is etched, which significantly lowers the yield. The second silicon oxide film 111 serves to prevent the patterned tungsten silicide shaped bitline 106 from being reflowed during the heat treatment at about 900 ° C. and at the same time not moved by possible stress. The second silicon oxide film 111 needs to improve the reliability of the packaged device (especially corrosion resistance to saline) if tungsten silicide is used in the adjacent circuit area as a fuse of the excess circuit.
Therefore, as shown in Fig. 6C, an accumulation node contact hole 114 is formed, and the buffered fluoric acid solution and the Branson cleaning liquid are allowed to penetrate into the substrate as a pretreatment process before the phosphorus-doped silicon film is formed. The purpose of these process steps is to strengthen the electrical connection between the substrate and the accumulation node and to increase the yield in part due to the particle removal effect. At this time, partly because the surface of the sidewall of the accumulation node forming contact hole 114 is slightly etched and the difference in the etch rate between the silicon oxide film and the BPSG film causes unevenness of several hundred angstroms in depth and height. do. Then, a 4000 angstrom phosphorus-doped silicon film is formed, patterned in a predetermined pattern, and eventually, an accumulation node 108 before HSG processing is formed.
Then, as shown in FIG. 6D, to remove the native oxide film from the surface of the accumulation node 108 of the phosphorus-doped silicon film and terminate the silicon surface by hydrogen atoms, that is, for HSG treatment, the silicon film surface Is treated with dilute fluoric acid, and treated with HSG by silane spinning and analysis to form irregularities on the surface of the accumulation node 108. Thereafter, the capacitor insulating film 115 and the plate electrode 116 of the in-doped silicon film are formed so that these two films are patterned in a predetermined pattern to obtain a capacitor over bitline structure memory cell.
However, attention is paid to the area excluding the memory cell, that is, the alignment mark used for mask alignment, and in particular the vernier mark which will be generally used from now on. In the conventional memory cell manufacturing method using the above-described HSG technology, the following problems are encountered. Will be hit.
The layout of the vernier mark is shown in FIG. 7A, where 201 indicates a pattern formed simultaneously with the accumulation node formation mask and 202 indicates a pattern formed simultaneously with the accumulation node formation mask.
In alignment marks, such as vernier marks, the arranged lower and upper layer patterns 201, 202 partially overlap each other, as shown in FIG. 7A. That is, it is possible to easily read out and obtain the difference value between alignment mark patterns by reading whether two patterns 201 and 202 in all the individual portions overlap or not.
Various problems with conventional manufacturing methods are as follows. FIG. 7B is a schematic cross-sectional view showing the shape of the vernier region during the manufacturing process corresponding to FIG. 6B, which is formed immediately after the third silicon oxide film 113.
As shown in Fig. 8A, a hole is formed simultaneously with the formation of the accumulation node forming contact hole 114 in the pattern 201 of Fig. 7A in the vernier region (i.e., the alignment region). As a pretreatment prior to the formation of the phosphorus-doped silicon film, when the substrate 100 is immersed in the buffered fluoric acid solution and the Branson cleaning solution, the sidewalls of the vernier region pattern 201, such as the memory cell region, are slightly etched and thereby several hundred angstroms. Depths and depths are provided. Then, an in-doped silicon film 108 for forming an accumulation node is also formed on the pattern 201.
As shown in FIG. 8B, simultaneously with the patterning of the phosphorus-doped silicon film 108 for formation of the accumulation node, the phosphorus-doped film 108 of the vernier region is also patterned using an anisotropic dry etch technique, FIG. The pattern 202 of 7a is formed. In the substrate 100, the recess 301 is formed by overetching the accumulation node, at which time the phosphorus-doped silicon film 108 of the sidewall surface of the recess having the unevenness is etched, and eventually, the phosphorus-doped. The sidewall 302 of the silicon film 108 is formed on the sidewall of the recess 301. In addition, since the side wall of the recess 301 has irregularities, the small side wall 302a and the large side wall 302b are formed to be separated from each other.
9A shows the structure of FIG. 8B surface treated with dilute fluoric acid. As described above, since the etch rate of the BPSG film to diluted fluoric acid is about several times that of the silicon oxide film, the etching of the BPSG films 110 and 112 on the sidewall surface of the recess 301 of the pattern 201 results in the sidewall 302. Proceeds from the uncovered part. Therefore, the small sidewall 302a is almost suspended in air, as shown in FIG. 9, and then, after HSG treatment, the portion is peeled off when treating waste (FIG. 9B), so that the yield is reduced.
As long as the BPSG film is not etched during the HSG pretreatment, only the sidewall 302 does not peel off and is left on the sidewall surface of the recess 301 in the pattern 201. In practice, however, the sidewall 302 was stripped off during HSG pretreatment with dilute fluoric acid. Nevertheless, HSG pretreatment with dilute fluoric acid is indispensable for the formation of good HSG type accumulation nodes.
Therefore, it is an object of the present invention to provide a semiconductor memory device in which the sidewalls do not peel off, and thus the yield is prevented from decreasing.
It is another object of the present invention to provide a method of manufacturing such a semiconductor memory device.
According to a first embodiment of the present invention, the first object is an HSG pretreated with a semiconductor substrate, a plurality of accessory patterns disposed on the semiconductor substrate, and an HSG preliminary process using dilute fluoric acid as an etching solution. and a plurality of accumulation nodes in the form of a hemispherical grained silicon film, which is obtained by a semiconductor memory device covering at least the sidewall surface of an accessory pattern.
Preferably, the accessory pattern is adjacent to each of the plurality of memory cell regions of the semiconductor substrate, and each accessory pattern has a double layer structure, which is when contact holes for the formation of accumulation nodes are formed in each memory cell region. And a first accessory pattern formed in the accessory pattern region and a second accessory pattern formed of a silicon film deposited to cover the first accessory pattern when the silicon film is filled in each of the contacts and formed in the form of an accumulation node.
In addition, the first accessory pattern is formed as a groove pattern, and the second accessory pattern is formed as a protruding pattern. The silicon forming the protruding pattern covers the sidewall surface of the groove pattern.
Alternatively, the portion of the first accessory pattern is covered with a silicon film formed in the form of an accumulation node, and the sidewall surface of the first accessory pattern is almost covered with a silicon film formed in the form of an accumulation node.
Preferably, the substrate is immersed in the buffered fluoric acid and the Branson washing liquid as a preliminary step before the phosphorus doped silicon film is formed. The silicon film is a phosphorus-doped silicon film.
According to a second embodiment of the present invention, the second object described above is a HSG (hemispherical grained) pretreated by an HSG pretreatment process using a semiconductor substrate, a plurality of accessory patterns disposed on the substrate, and dilute fluoric acid as an etchant. A method of manufacturing a semiconductor device having a plurality of accumulation nodes in the form of a silicon film, the method comprising the steps of forming an accumulation node forming contact hole in a semiconductor substrate, and including an accessory pattern and an accumulation node forming contact hole. Forming an accumulation node forming semiconductor material film in its entirety and patterning the accumulation node forming semiconductor material film formed on the accumulation node forming contact hole to cover the sidewall surface of the accessory pattern. Obtained by the method.
Preferably, the accessory pattern is adjacent to each of a plurality of memory cell regions of the semiconductor substrate, each of the accessory patterns on the semiconductor substrate having a dual structure having a first and a second accessory pattern, wherein the patterning step comprises an accumulation node Forming a first accessory pattern in each of a plurality of subregions adjacent to each memory cell region during formation of the formation contact hole, and accumulating node forming semiconductors on the first accessory pattern in the accessory pattern region as well as the memory cell region Forming a material film, and forming a second accessory pattern by patterning an accumulation node forming semiconductor material film in the accessory pattern region in a form sufficient to cover the sidewalls of the first accessory pattern.
According to a third embodiment of the present invention, the above-described second object is an HSG preprocessed as an HSG preliminary procedure using a semiconductor substrate, a plurality of accessory patterns disposed on the substrate, and dilute fluoroacid as an etching solution. obtained by another method of manufacturing a semiconductor memory device having a plurality of accumulation nodes in the form of a (hemispherical grained) silicon film, the method comprising: forming an accumulation node forming contact hole in a semiconductor substrate; Forming an accumulation node forming semiconductor material film on the semiconductor substrate throughout the accumulation node forming contact hole, and in such a manner that successive sidewalls of the accumulation node forming semiconductor material are formed on the respective sidewall surfaces of the accessory pattern. Patterning an accumulation node forming semiconductor material film formed on the substrate.
As described above, according to the prior art, a projecting pattern as the second accessory pattern is formed at a position away from the sidewall of the groove pattern as the first accessory pattern.
In the present invention, in order to remove the sidewall peeling, a protruding pattern of the accumulation node forming film is formed to cover the sidewall surface of the groove pattern.
The above and other objects, advantages and features of the present invention will become more apparent when described in conjunction with the accompanying drawings.
1A is a schematic plan view illustrating a protrusion pattern formed in each alignment area in a semiconductor memory device according to a first embodiment of the present invention.
1B is a schematic plan view showing a groove pattern formed in the alignment region in the semiconductor memory device of the first embodiment.
2 is a schematic plan view showing a modification of the pattern of the first embodiment.
3A to 3D are partial schematic cross-sectional views showing the process sequence of the first manufacturing method according to the first embodiment.
4A and 4B are partial schematic cross-sectional views showing a process sequence of a second manufacturing method according to the second embodiment.
5A is a schematic plan view of a conventional semiconductor memory device.
FIG. 5B is a schematic cross-sectional view taken along the line AA ′ of FIG. 5A.
6A-6D are schematic cross-sectional views showing a process sequence of a conventional manufacturing method for a conventional semiconductor memory device.
FIG. 7A is a schematic plan view showing a protrusion pattern and a groove pattern formed in the alignment area when they are deviated from each other in the conventional manufacturing method. FIG.
7B is a schematic cross-sectional view showing the shape of an alignment region in an intermediate process step of a conventional manufacturing method.
8A and 8B are enlarged schematic cross-sectional views taken along the line CC ′ of FIG. 7A, illustrating the problems with the prior art.
9A and 9B are enlarged cross-sectional views similar to FIGS. 8A and 8B, illustrating another problem with the prior art.
Explanation of symbols on the main parts of the drawing
100: silicon substrate 101: device isolation region
108: accumulation node 110: insulating film
112: BPSG membrane
The principle of the present invention is particularly useful when applied to a semiconductor memory device and a manufacturing method thereof, and a preferred embodiment thereof will be described in detail with reference to the accompanying drawings.
First embodiment
1A and 1B are schematic plan views of first and second alignment marks used in a semiconductor memory device according to a first embodiment of the present invention, respectively.
The semiconductor memory device of the first embodiment has a plurality of memory cell regions and a plurality of accessory pattern regions (hereinafter referred to as alignment regions) arranged adjacent to each memory cell region on the semiconductor memory device. In this embodiment, the first and second alignment (placement) marks will be described as first and second accessory patterns.
As shown in Fig. 1A, a first alignment mark is formed in each alignment region as a groove pattern 201 when an accumulation node forming contact hole is formed in each memory cell region.
As shown in FIG. 1B, the second alignment mark is deposited on the sidewall surfaces of all the groove patterns 201 when the film filled in all the accumulation node forming contact holes is formed in the expected accumulation node shape. ) Is formed in each alignment area as a projecting pattern of (shown as diagonal lines).
In the present embodiment, grooves and protrusion patterns 201 and 202 formed simultaneously using the accumulation node formation mask are entirely covered by the accumulation node formation film 108, and the sidewalls are covered by the accumulation node formation film 108. It is not formed on any sidewall surface of the grooves and protruding patterns 201, 202, so that no traces, such as stripped sidewall pieces, occur during the formation of the expected HSG type accumulation node.
2 shows a variation of the first embodiment. In the present modification, although the groove pattern 201 is only partially covered by the accumulation node forming film 108, the sidewall surface of the groove pattern 201 formed simultaneously using the accumulation node forming mask is formed by the accumulation node. Since covered entirely with the formation film 108, sidewall peeling does not appear during the process of formation of the expected HSG type accumulation node as in the first embodiment of Figs. 1A and 1B.
The manufacturing method of the semiconductor memory device of the above embodiment will be described with reference to Figs. 3A to 3F. 3A and 3B are enlarged schematic cross-sectional views taken on line C-C 'showing the process sequence of manufacture.
3a shows the same process steps as in FIG. 10a of the prior art. As shown in Fig. 3A, in order to form the accumulation node formation contact hole in the memory cell region in the multilayer insulating film, after the groove pattern 201 is formed in the alignment region, the silicon film 108 which is doped with the substrate 100 is formed. In the previous pretreatment, the phosphorus-doped silicon film 108 for the expected accumulation node was formed as a groove pattern 201 in the alignment region including the memory cell region, soaked in the Brason cleaning liquid and buffered fluoric acid.
Then, as shown in FIG. 3B, in the alignment region, the in-doped silicon film 108 for formation of the expected accumulation node is patterned in the shape of the protruding pattern 202 of FIG. 2. At this time, since the accumulation node formation film 108 on the sidewall surface of the groove pattern 201 corresponding to the accumulation node contact pattern in the alignment region is not etched, the sidewall of the accumulation node formation film 108 is formed on the sidewall surface. It doesn't work. In particular, in the alignment region, the phosphorus-doped silicon film 108 for formation of the expected accumulation node is patterned to cover the sidewall surface of the groove pattern, so that sidewall peeling of the phosphorus-doped silicon film 108 does not appear. In this embodiment, as in the prior art, even though the overetching portion 304 is present in the silicon substrate as a result of the overetching of the expected accumulation node, the portion 304 does not adversely affect the yield.
Subsequently, the surface treatment is performed with dilute hydrofluoric acid, as shown in FIG. 3C. At this time, etching of the BPSG films 110 and 112 on the sidewall surface of the groove pattern 201 with dilute fluoric acid proceeds from the portion remaining uncovered by the accumulation node forming film 108. Nevertheless, as shown in FIG. 3D, a single continuous piece of the accumulation node forming film 108 is in intimate contact with the silicon substrate 100 as well as the silicon oxide films 101 and 111, so that any portion of the sidewall portion is not in contact with the silicon substrate 100. It is not suspended in air and does not peel off even after subsequent HSG treatment.
Second embodiment
4A and 4B are schematic cross-sectional views showing the process sequence of the manufacturing method according to the second embodiment.
4a shows the same process steps corresponding to FIG. 10a of the prior art. As shown in FIG. 4A, in order to form the accumulation node forming contact hole in the memory cell region in the multilayer insulating film, the groove pattern 201 is formed in the alignment region and then the substrate 100 is formed with the in-doped silicon film 108. As a pretreatment prior to soaking, it is immersed in buffered fluoric acid and Brason washing liquid. At this time, the sidewall surface of the groove pattern 201 is slightly etched to form unevenness, and an in-doped silicon film 108 for the expected accumulation node is formed to cover the memory cell region and the alignment region.
As shown in FIG. 4B, in the alignment region, at the same time as the patterning of the phosphorus-doped silicon film 108 for formation of the expected accumulation node, the phosphorus-doped silicon film 108 is in the shape of the protruding pattern 202. Patterned. At this time, since the accumulation node formation film 108 on the sidewall surface of the groove pattern 201 corresponding to the accumulation node contact pattern in the alignment region is etched, the sidewall 108a of the accumulation node formation film 108 is on the sidewall surface. Is formed. Etch residues do not appear, and the etching conditions of the accumulation node material are controlled such that the sidewalls 108a formed on the irregular sidewall surface are continuous without being separated at the boundary of the uneven portion.
In this embodiment, the accessory patterns are alignment marks for placement. These accessory patterns are by no means limited to alignment marks, but may be vernier patterns, box patterns, etch patterns or various other patterns.
According to the present invention, since the sidewall surface of the individual accessory pattern is covered with the accumulation node forming film, the sidewall is not formed on the sidewall surface of the accessory pattern even immediately after the surface treatment is performed with dilute fluoric acid as the HSG pretreatment. The fall of a yield can be prevented by side wall peeling.
In addition, since the accumulation node semiconductor material formed throughout the accumulation node forming contact is patterned so that continuous sidewalls are formed in intimate contact with the sidewall surface of the accessory pattern, the sidewall pieces do not float in the air during the residue treatment, so that sidewall peeling is performed. The yield can be prevented from decreasing.
The present invention is in no way limited to the above-described embodiments, and various modifications and changes may be proposed in a range that does not depart from the spirit and scope of the present invention. Finally, this application takes priority of Japanese Patent Application No. 9-102192, filed April 18, 1997, which is incorporated herein by reference.

权利要求:
Claims (20)
[1" claim-type="Currently amended] A semiconductor substrate,
A plurality of accessory patterns disposed on the semiconductor substrate,
Including a plurality of accumulation nodes in the form of HSG silicon film that has been pretreated by an HSG (hemispherical grained) preprocess using dilute fluoric acid as an etching solution,
And the silicon film covers at least a sidewall surface of the accessory pattern.
[2" claim-type="Currently amended] The semiconductor device of claim 1, wherein the accessory pattern is adjacent to a plurality of memory cell regions of the semiconductor substrate.
Each of the accessory patterns having a double layer structure,
A first accessory pattern formed in the accessory pattern region when a contact hole for forming the accumulation node is formed in each of the memory cell regions;
And a second accessory pattern formed of the silicon film deposited to cover the first accessory pattern when the silicon films are filled in each of the contacts and formed in an accumulation node shape.
[3" claim-type="Currently amended] The semiconductor memory device of claim 2, wherein the first accessory pattern is formed in a groove pattern, and the second accessory pattern is formed in a protruding pattern.
[4" claim-type="Currently amended] The semiconductor memory device of claim 3, wherein the silicon forming the protruding pattern covers a sidewall surface of the groove pattern.
[5" claim-type="Currently amended] 3. The method of claim 2, wherein only a part of the first accessory pattern is covered by the silicon film formed in the form of the accumulation node, and the sidewall surface of the first accessory pattern is entirely covered by the silicon film formed in the form of the accumulation node. A semiconductor memory device characterized by the above-mentioned.
[6" claim-type="Currently amended] 2. The semiconductor memory device according to claim 1, wherein before the phosphorus-doped silicon film is formed, the substrate is immersed in a buffered fluoric acid and a Branson cleaning solution as the preceding process.
[7" claim-type="Currently amended] The semiconductor memory device of claim 1, wherein the silicon film is a doped silicon film.
[8" claim-type="Currently amended] A semiconductor memory having a semiconductor substrate, a plurality of accessory patterns disposed on the substrate, and a plurality of accumulation nodes in the form of an HSG silicon film which is pretreated by an HSG (hemispherical grained) preprocess using dilute fluoric acid as an etching solution. In the method of manufacturing the device,
(a) forming an accumulation node forming contact hole in the semiconductor substrate;
(b) forming an accumulation node forming semiconductor material film on the semiconductor substrate over the accessory pattern and the accumulation node forming contact hole;
(c) patterning an accumulation node forming semiconductor material film formed on the accumulation node forming contact hole and adapted to cover the sidewall surface of the accessory pattern.
[9" claim-type="Currently amended] The method of claim 8, wherein the accessory pattern is adjacent to each of the plurality of memory cell regions of the semiconductor substrate, each of the accessory pattern on the semiconductor substrate has a double layer structure consisting of the first and second accessory pattern,
The patterning step,
Forming a first accessory pattern in each of the plurality of accessory regions adjacent to each memory cell region during the formation of the accumulation node forming contact hole;
Forming an accumulation node forming semiconductor material film over the first accessory pattern of the memory cell region and the accessory pattern region;
And forming a second accessory pattern by patterning the accumulation node forming semiconductor material film in the accessory pattern region in a shape to cover the sidewall surface of the first accessory pattern.
[10" claim-type="Currently amended] 10. The method of claim 9, wherein each of the first accessory patterns is formed in a groove pattern, and each of the second accessory patterns is formed in a protrusion pattern.
[11" claim-type="Currently amended] The method of claim 10, wherein the silicon forming the protruding pattern covers a sidewall surface of the groove pattern.
[12" claim-type="Currently amended] 10. The semiconductor device of claim 9, wherein only a part of the first accessory pattern is covered by the silicon film formed in the form of the accumulation node, and the sidewall surface of the first accessory pattern is entirely covered by the silicon film in the form of the accumulation electrode. A method of manufacturing a semiconductor memory device, characterized in that.
[13" claim-type="Currently amended] 9. A method according to claim 8, wherein the substrate is immersed in a buffered fluoric acid and a Brason cleaning solution as the preceding step before the silicon film is formed.
[14" claim-type="Currently amended] The method of claim 8, wherein the silicon film is a phosphorus-doped silicon film.
[15" claim-type="Currently amended] Fabrication of a semiconductor memory device having a semiconductor substrate, a plurality of accessory patterns disposed on the substrate, and a plurality of accumulation nodes in the form of an HSG silicon film pretreated by an HSG (hemispherical grained) preprocess using dilute fluoric acid as an etching solution In the method,
(a) forming an accumulation node forming contact hole in the semiconductor substrate;
(b) forming an accumulation node forming semiconductor material film on the semiconductor substrate over the accessory pattern and the accumulation node forming contact hole;
(c) patterning an accumulation node forming semiconductor material film formed on the accumulation node forming contact hole in such a manner that a continuous sidewall of the accumulation node forming semiconductor material is formed at each side wall surface of the accessory pattern. A method of manufacturing a semiconductor memory device, characterized in that.
[16" claim-type="Currently amended] The semiconductor device of claim 15, wherein the accessory pattern is adjacent to each of a plurality of memory cell regions of the semiconductor substrate, and each of the accessory patterns on the semiconductor substrate has a double layer consisting of first and second accessory patterns.
The patterning step,
Forming a first accessory pattern in each of the plurality of accessory regions adjacent to each memory cell region during the formation of the accumulation node forming contact hole;
Forming an accumulation node forming semiconductor material film over the first accessory pattern of the memory cell region and the accessory pattern region;
And forming a second accessory pattern by patterning the accumulation node forming semiconductor material film in the accessory pattern region in a shape so as to cover the sidewall surface of the first accessory pattern.
[17" claim-type="Currently amended] The method of claim 16, wherein each of the first accessory patterns is formed in a groove pattern, and each of the second accessory patterns is formed in a protrusion pattern.
[18" claim-type="Currently amended] 18. The method of claim 17, wherein the silicon forming the protruding pattern covers a sidewall surface of the groove pattern.
[19" claim-type="Currently amended] 17. The method of claim 16, wherein only a part of the first accessory pattern is covered with the silicon film formed in the form of the accumulation node, and the sidewall surface of the first accessory pattern is entirely covered with the silicon film formed in the form of the accumulation node. A semiconductor memory device manufacturing method characterized by the above-mentioned.
[20" claim-type="Currently amended] 16. The method of manufacturing a semiconductor memory device according to claim 15, wherein the substrate is immersed in a buffered fluoric acid and a Brason cleaning solution as the preceding step before the silicon film is formed.

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同族专利:

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公开号 | 公开日

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US6097054A|2000-08-01|

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TW454235B|2001-09-11|

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JPH10294439A|1998-11-04|

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JP3039438B2|2000-05-08|

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US6368934B1|2002-04-09|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1997-04-18|Priority to JP97-102192

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1997-04-18|Priority to JP9102192A

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1998-04-17|Application filed by 가네꼬히사시, 닛뽕덴끼가부시끼가이샤

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1998-11-25|Publication of KR19980081520A

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2001-10-19|Application granted

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2001-10-19|Publication of KR100304134B1

优先权:

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申请号 | 申请日 | 专利标题

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JP97-102192|1997-04-18|

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JP9102192A|JP3039438B2|1997-04-18|1997-04-18|Semiconductor memory device and method of manufacturing the same|